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2009 News
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2010
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2009
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2002
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Sigrity Announces XtractIMTM Version 3.0 for IC Package Modeling
-- Next-generation assessment capabilities enable Altera,
Qualcomm, others to rapidly and fix performance issues
--July 22, 2009
Powerful new features move XtractIM
into its own category. XtractIM continues to offer
the fastest and most accurate package extraction available
for the full range of IC package types from leadframe
designs to multi-die SiP implementations. Package models
can be created that are accurate over broadband frequencies.
With 3.0 XtractIM provides immediate feedback specific areas
of package vulnerability to enable rapid improvement.
Press Release
High Resolution Images
Presentation: Performance Assessment with XtractIM
Additional XtractIM Information |
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Sigrity introduces SpeedXP
9.0 production
--June 19, 2009
The 9.0 release includes accuracy refinements to help users
tackle the most challenging power integrity and signal
integrity issues associated in their leading edge designs.
Users of SPEED2000, PowerSI, PowerDC, Broadband SPICE and
Channel Designer will see ease-of-use enhancements as well.
Support is provided for users on both Windows and Linux
platforms. |
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Sigrity introduces SpeedXP 9.0 beta
--May 8, 2009
Capabilities are particularly focused
on simplifying design flow integration
and enhanced user productivity. As always, the release
includes accuracy refinements to help users tackle the most
challenging power integrity and signal integrity issues
associated in their leading edge designs. 9.0 beta
includes enhancements for users of SPEED2000, PowerSI,
PowerDC, Broadband SPICE and Channel Designer. Support
is provided for users on both Windows and Linux platforms.
(more) |
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Sigrity's Channel Designer Wins the Printed Circuit Design & Fab Magazine New Product Introduction Award
--March 30, 2009
This was the first year for the award and Sigrity's win
was in the category of System Modeling / Verification Tools.
Sigrity was sole EDA company winner. Channel Designer provides
signal integrity assurance to design teams developing systems that
include high-speed serial links which are fast becoming the backbone
of modern interconnect. Chip design teams use Channel Designer as they
create transmitter and receiver models. Package and board teams use Channel
Designer to ensure channel jitter and noise stay within data sheet tolerances by accurately
predicting bit error rate (BER) and crosstalk.
(more) |
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Teklatech's FloorDirector Tool Compatible with Sigrity's XcitePI Power Integrity Simulation Flow
--February 24, 2009
IC designers using Sigrity's XcitePI and Teklatech's FloorDirector benefit from an
integrated flow. The flow addresses handling dynamic IR drop
issues particularly for complex nanometer designs.
(more) |
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Sigrity Unveils Breakthrough Channel Designer Solution
--January 20, 2009
With operating rates approaching 10 gigabits per second, high-speed serial
links are very susceptible to jitter and noise. The Channel Designer™
analysis environment offers an easily used schematic editor,
automated model connection, IBIS Algorithmic Modeling Interface
(AMI) support, and the most accurate channel characterization
available. This precision is critical to accurately predict bit
error rate (BER) to ensure reliable system operation across the
DC to multi-gigahertz spectrum.
Press Release
High Resolution Images
Additional Channel Designer Information |
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